FET adaptive limiter with high current FET detector
US5157289A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 29, 1991 |
| Grant date | Oct 20, 1992 |
| Priority date | — |
| Expiry date | Jul 29, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An adaptive power limiter circuit for suppressing power spikes output by a receiver to reduce the chances of damage to the receiver includes a first attenuating stage having an input terminal for receiving power spikes of input magnitude. A first FET is coupled to the input terminal and an output terminal is coupled to the first FET for providing power spikes of output magnitude which are diminished in power relative to the input magnitude. A second attenuating stage has an input terminal connected to the output terminal of the first attenuating stage for receiving the power spikes output by the first stage, an additional FET is coupled to the input terminal of the second stage and a second stage output terminal is coupled to the additional FET for providing power spikes of output magnitude which are considerably diminished in power relative to the input magnitude of the spikes at the input terminal of the first stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.