Variable decimation architecture for a delta-sigma analog-to-digital converter
US5157395A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 4, 1991 |
| Grant date | Oct 20, 1992 |
| Priority date | — |
| Expiry date | Mar 4, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H17/0664
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An analog-to-digital converter includes a delta-sigma modulator (10), having the output thereof filtered by a digital filter section. The digital filter section includes a first fixed decimation filter (12) followed by a variable decimation filter section (14) and an output low-pass filter section (16), having a fixed decimation ratio. The fixed variable decimation filter section (14) includes a single FIR filter (24) that has data processed therethrough with different sampling rates. A recursive controller (26) receives an external configuration input to determine the number of passes through the filter (24) that are required to provide the desired decimation ratio.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.