Semiconductor memory
US5157628A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 10, 1990 |
| Grant date | Oct 20, 1992 |
| Priority date | — |
| Expiry date | Aug 10, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/846
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory in which a normal memory area is divided into a plurality of divided memory areas, a data buffer is provided for each of the divided memory areas, the bit lines of each divided memory area is connected via column selector to a data buffer corresponding to the divided memory area, a buffer changeover switching means is connected between each data buffer and the data bus, a column accessing is made by turning the buffer changeover switching means in a predetermined sequence while said column selector is controlling by output signals of the column decoder decoding the column address signals, is disclosed. The above mentioned semiconductor memory is so designed that, for rescuing the bit in trouble without uselessly increasing the area, a redundancy memory area and a redundancy data buffer are provided which are connected via the redundancy select switching means, said redundancy select switching means is turned on by an address comparator circuit when the column address in trouble coincides with the column address signal, and that the redundancy data buffer is connected to the data bus when the buffer changeover switching means connected to the data buffer corre…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.