DRAM having extended refresh time
US5157634A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 1990 |
| Grant date | Oct 20, 1992 |
| Priority date | — |
| Expiry date | Oct 23, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A DRAM is described including a plurality of operable storage cells, each cell including a capacitance for storing a charge indicative of data. The charge tends to dissipate below an acceptable level after a predetermined time interval T1 for a majority of the operable cells and for a minority of the operable cells, it dissipates below the acceptable level after a shorter time interval T2. The time between DRAM refresh cycles is adjusted so as to be greater than time interval T2. The DRAM comprises: a plurality of redundant storage cells; a decoder for receiving the address of an operable memory cell and providing a first output if the address indicates one of the operable cells of the minority of cells and a second output if the address indicates one of the operable cells of the majority. A switching circuit is responsive to the first output to enable access of a redundant stoarge cell and to prevent access of the minority storage cell. In a preferred embodiment, the redundant storage cells are configured as static storage circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.