Apparatus for generating a DS-3 signal from the data component of an STS-1 payload signal
US5157655A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 1990 |
| Grant date | Oct 20, 1992 |
| Priority date | — |
| Expiry date | Oct 31, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2205/061
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An apparatus which receives a gapped data component of an STS-1 signal and provides therefrom an ungapped DS-3 data signal is provided and includes a FIFO for receiving the data component of the STS-1 signal, a measuring circuit having an input clock related to the STS-1 signal and the output clock of the apparatus as inputs for effectively measuring the relative fullness of the FIFO, and a voltage controlled crystal oscillator (VCXO) for receiving a control signal from the measuring circuit and for generating the output clock of the apparatus in response thereto, where data in the FIFO is taken out of the FIFO as the DS-3 signal according to the rate of the output clock. The FIFO is preferably a byte wide RAM, and the measuring circuit is comprised of two counters, an XOR gate, and a low pass filter. One counter receives the apparatus output clock as its input, while the other counter receives a gapped STS-1 data payload input clock as its input. The msb's of the counters are compared by the XOR gate, and the duty cycle of the XOR gate output provides an indication of the difference between the rates of the input and output clocks. The low pass filter filters out high frequency ch…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.