Data processor test architecture
US5157781A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 2, 1990 |
| Grant date | Oct 20, 1992 |
| Priority date | — |
| Expiry date | Jan 2, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2221
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A test architecture in a data processing system having a plurality of circuit portions, coupled via a communication bus. In the system, a dedicated test register is placed in predetermined circuit portions which each can then operate in a normal mode and a test mode. A central processing unit (CPU) may initiate a test operation in any of the circuit portions in response to software executing by writing an operand to a centralized test module. Operands are scanned into and out of a circuit portion being tested while the central processing unit is capable of performing non-test processing activites. The CPU may also test itself using a dedicated test register which can only cause the CPU to enter a test mode after the register is written to.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.