Method of burn-in testing of circuitry
US5157829A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 1990 |
| Grant date | Oct 27, 1992 |
| Priority date | — |
| Expiry date | Oct 2, 2010 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49155
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of burn-in testing circuitry, the method comprising the steps of providing a single printed circuit board substrate having first and second sections, defining, after the substrate providing step, a plurality of discrete circuits on respective portions of the first section of the single printed circuit board substrate, forming, after the defining step, conductive traces and an edge connector on the second section of the printed circuit board substrate, the traces starting from the circuits and ending at the edge connector on the printed circuit board substrate, the printed circuit board substrate, the circuits, the traces, and the edge connector defining a printed circuit board, and the edge connector having conductive portions respectively connected to the circuits by the traces, providing a burn-in test unit adapted to receive the printed circuit board and to interface with the edge connector for burn-in testing of the circuits on the printed circuit board substrate, inserting, after the forming and test unit providing steps, the printed circuit board into the burn-in test unit such that the burn-in test unit interfaces with the edge connector, and causing, after the inse…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.