Structure and method for preventing latch-up in integrated circuits
US5159204A · kind A · utility
7Cited by
8References
24Claims
0Family size
Inventors
Key dates
| Filing date | Nov 18, 1987 |
| Grant date | Oct 27, 1992 |
| Priority date | — |
| Expiry date | Nov 18, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit and method for avoiding latch up in an integrated circuit in which the base-emitter junction of a parasitic bipolar transistor forming part of a parasitic SCR structure is monitored. If the forward bias of the monitored base-emitter junction approaches a predetermined value, the operation of the circuit is altered to prevent activation of the SCR.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.