Timing generator circuit including adjustable tapped delay line within phase lock loop to control timing of signals in the tapped delay line
US5159205A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 1990 |
| Grant date | Oct 27, 1992 |
| Priority date | — |
| Expiry date | Oct 24, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/15033
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit for generating a plurality of timing signals includes a plurality of cascade-connected delay cells, each having an input coupled to an output of another, and a plurality of latches. Set inputs of various latches are coupled to outputs of various delay cells to determine times of occurrence of leading edges of various timing pulses. Reset inputs of the various latches are coupled to outputs of various delay cells to determine times of occurrence of trailing edges of various timing pulses. The circuit includes a phase detector having a first input coupled to receive a clock signal and a second input coupled to an output of one of the delay cells to receive a signal indicative of propagation of a logic state through a first group of the delay cells, to produce an adjustment signal indicative of whether the phase of the indicator signal is ahead of or behind the phase of the clock signal. Each of the delay cells increases or decreases propagation time through that delay cell in response to the adjustment signal, so as to cause a time required for the logic state to propagate through all of the delay cells to be equal to a period of the clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.