Sidewall-sealed poly-buffered LOCOS isolation
US5159428A · kind A · utility
22Cited by
5References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 5, 1990 |
| Grant date | Oct 27, 1992 |
| Priority date | — |
| Expiry date | Dec 5, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This is a semiconductor device, comprising: a semiconductor body having an isolation region separating at least two active device regions; pad oxide layers disposed on said active regions; polysilicon layers disposed on said pad oxide layers; silicon nitride layers disposed on said polysilicon layers; and a sidewall seal disposed all along the perimeter of the active device regions to seal said active device regions against oxygen diffusion. The resulting field oxide isolation region has reduced oxide encroachment into the active moat region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.