High speed testing for programmable logic devices
US5159599A · kind A · utility
5Cited by
5References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 31, 1990 |
| Grant date | Oct 27, 1992 |
| Priority date | — |
| Expiry date | Jul 31, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318516
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A shift register used to shift programming and test data into a programmable logic device is modified so that each bit thereof can be directly set or reset. Control signals can be used to directly place the required test patterns into the shift register. A memory connected to the shift register, and associated logic, provides a means for testing whether data was accurately written to the array without shifting any data off of the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.