CMOS shift register with complementary refresh pass gates and buffer
US5159616A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 1990 |
| Grant date | Oct 27, 1992 |
| Priority date | — |
| Expiry date | Oct 25, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C19/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The improved CMOS shift register consists of a series of alternating PMOS and NMOS pass gates driven by a single clock signal. Each gate consists of either one or more PMOS transistor(s), or one or more NMOS transistor(s). When the clock signal goes low, the PMOS gates turn on and pass bit values. At the same time the adjacent NMOS gates, which are driven by the same low clock signal, shut off and prevent the passed bit values from traveling any further. The bit values are thus held between adjacent PMOS and NMOS gates. When the clock signal next goes high, the NMOS gates turn on and pass the held bit values while the PMOS gates driven by the same high clock shut off. The gates are connected by circuitry which essentially holds the bit values passed through the first associated gate until they are passed through the second associated gate. The shift register may also include gated or non-gated refresh circuitry, which operates to maintain a passed bit value. The refresh circuitry may include gates which are the complements of the associated pass gates, with all the gates driven by the same clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.