System and method for dynamic avoidance of a simultaneous switching output limitation of a integrated circuit chip
US5160922A · kind A · utility
8Cited by
5References
42Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 29, 1990 |
| Grant date | Nov 3, 1992 |
| Priority date | — |
| Expiry date | Jun 29, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/364
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for limiting the number of simultaneously switching outputs of an integrated circuit chip to at or below a predetermined limit for the chip during a short, predetermined time window by dynamically arbitrating request signals from discrete on-chip logic elements for assignment of output pins according to the priority of the request signals based on the type and intended use of output signals from such elements, and the immediate state of the integrated circuit chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.