Multiprocessing packet switching connection system having provision for error correction and recovery
US5161156A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 2, 1990 |
| Grant date | Nov 3, 1992 |
| Priority date | — |
| Expiry date | Feb 2, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1423
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A large number of processing elements (e.g. 4096) are interconnected by means of a high bandwidth switch. Each processing element includes one or more general purpose microprocessors, a local memory and a DMA controller that sends and receives messages through the switch without requiring processor intervention. The switch that connects the processing elements is hierarchical and comprises a network of clusters. Sixty-four processing elements can be combined to form a cluster and sixty four clusters can be linked by way of a Banyan network. Messages are routed through the switch in the form of packets which include a command field, a sequence number, a destination address, a source address, a data field (which can include subcommands), and an error correction code. Error correction is performed at the processing elements. If a packet is routed to a non-present or non-functional processor, the switch reverses the source and destination field and returns the packet to the sender with an error flag. If the packet is misrouted to a functional processing element, the processing element corrects the error and retransmits the packet through the switch over a different path. In one embodim…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.