Circuit and method of detecting an invalid clock signal
US5161175A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 28, 1991 |
| Grant date | Nov 3, 1992 |
| Priority date | — |
| Expiry date | May 28, 2011 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S331/02
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A phase lock loop monitors the frequency of redundant input clock signals and switches back and forth therebetween should one or the other become invalid. Thus, the PLL may continue normal operation even with a failure of one input clock signal. If both the input clock signals fail, an internal reference signal maintains the PLL at a nominal operating frequency until one of the input clock signals is restored whereby the loop can quickly re-establish phase lock. To determined validity, the input clock signals are sampled and stored by the reference signal in a predetermined manner. The input clock signal is valid if the samples of the input clock signal each have the same logic state after the sampling period; otherwise, the input clock signal is invalid if the samples of the input clock signal have at least one different logic state after the sampling period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.