Pipelined cryptography processor and method for its use in communication networks
US5161193A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 1990 |
| Grant date | Nov 3, 1992 |
| Priority date | — |
| Expiry date | Jun 29, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/125
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
Cryptographic apparatus, and a related method for its operation, for in-line encryption and decryption of data packets transmitted in a communication network. A full-duplex cryptographic processor is positioned between two in-line processing entities of a network architecture. For example, in a fiber distributed data interface (FDDI) network, the processor is positioned between a media access control (MAC) sublayer and a ring memory controller (RMC). Incoming information packets are analyzed to decide whether or not they contain encrypted data and, if they do, are subject to decryption before forwarding. Outbound information packets have their data portions encrypted if called for, and are usually forwarded toward the network communication medium. Cryptographic processing in both directions is performed in real time as each packet is streamed through the processor. The processing of outbound information packets includes using optional data paths for looping of the processed information back in a reverse direction, to permit the host system to perform local encryption or decryption for various purposes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.