Digitally controlled crystal-based jitter attenuator
US5162746A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 7, 1990 |
| Grant date | Nov 10, 1992 |
| Priority date | — |
| Expiry date | Aug 7, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit for attenuating phase jitter on an incoming clock signal includes a digitally controlled oscillator, a phase lock loop including a phase detector, and a dithering circuit. The oscillator is capable of generating N discrete frequencies selectable through digitally controlled inputs controlling switched, capacitively-loaded amplifier stages. The phase lock loop provides a total of C.times.N.times.NB frequencies. The phase detector consists primarily of an up/down counter with an overflow/underflow limiter circuit. The dithering circuit modulates the oscillator signal to reduce inadequate rejection behavior when the incoming clock frequency is substantially the same as one of the N selectable frequencies of the oscillator divided down to match the frequency of the incoming clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.