Semiconductor integrated circuit device with an enlarged internal logic circuit area
US5162893A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 7, 1991 |
| Grant date | Nov 10, 1992 |
| Priority date | — |
| Expiry date | Mar 7, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/998
Abstract
A semiconductor integrated circuit device includes a semiconductor chip, and bonding pads used for interfacing with an external device. The bonding pads are arranged in an outer portion of a chip peripheral area on the semiconductor chip. A pair of N-channel and P-channel transistor areas is provided for two or more neighboring bonding pads among the bonding pads, and is arranged in the vicinity of the two or more neighboring bonding pads in the chip peripheral area. The pair of N-channel and P-channel transistor areas is used for forming a peripheral circuit used for interfacing with the external device through the related two or more bonding pads. The peripheral circuit related to the two or more neighboring bonding pads is formed by the pair of N-channel and P-channel transistor areas.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.