Paired bit error rate tester
US5163051A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 2, 1990 |
| Grant date | Nov 10, 1992 |
| Priority date | — |
| Expiry date | Feb 2, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/24
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A Bit Error Rate (BER) test arrangement, composed of two autonomous BER test systems, effects the full-duplex testing of a pair of co-located modems terminating a simulated transmission link by utilizing a single processor to control each independent BER test system and a buffer storage device, preferably a dual-port random access memory and a multiple access memory serving each of the test systems, to post information communicated between the controller processor and each of the test systems. This arrangement minimizes duplication of circuitry by assigning basically identical processing operations of the individual test systems to the single processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.