Digital data synchronizer
US5163070A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 1990 |
| Grant date | Nov 10, 1992 |
| Priority date | — |
| Expiry date | Dec 7, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/043
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A digital data synchronizer, synchronizes a digital data system to an incoming serial bit stream having a segment of pseudo random bit sequence, which is a function of a predetermined primitive polynomial, preceeding the start of data. The synchronizer includes a first feedback shift register configured as a multiplier for generating the pseudo random bit sequence. The multiplier register operates on the incoming serial bit stream to determine whether a valid bit sequence of the primitive polynomial is present in the incoming serial bit stream, and if it is, a zero output is produced. A second feedback shift register configured as a divider produces a pseudo random bit sequence which is also a function of the predetermined primitive polynomial. A counter is provided to monitor the number of zeros outputted by the multiplier feedback shift register. When a preset count is reached, the contents of the multiplier shift register is parallel loaded into the divider shift register if the bit sequence of the divider shift register does not match the bit sequence of the incoming serial data. Thus, the divider pseudo random sequence is synchronized to the incoming serial data. A synch word …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.