Parallel scrambler used in sonet data transmission
US5163092A · kind A · utility
22Cited by
5References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 28, 1990 |
| Grant date | Nov 10, 1992 |
| Priority date | — |
| Expiry date | Nov 28, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03872
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A data scrambler circuit which adds the SONET polynomial 1+X.sup.6 +X.sup.7 to data in a parallel format to thereby reduce circuitry clock rates to one-eighth the line rate, which reduces power consumption and simplifies timing constraints. A circuit embodiment includes a first series of flip-flops connected to generate the polynomial and a second series of flip-flops for holding the generated polynomial. The parallel data is added to the held polynomial by a series of exclusive OR gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.