Image processing circuit with reduced number of contact pads
US5163100A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 2, 1991 |
| Grant date | Nov 10, 1992 |
| Priority date | — |
| Expiry date | Apr 2, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T5/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit for the processing of digitized signals which are representative of a source image which is defined by image elements which are encoded on M bits and which are arranged in I rows and J columns. The image is processed by means of M sliding windows (W.sub.1 to W.sub.M) which consist of N rows and P columns and which step-wise slide past each image element along I rows, but which have been shifted through one row with respect to one another. Processing is performed by bit serial operators which successively act on the bits of each of the N+N-1 image elements. The signals may be serially applied via Q contact pads, where Q=N+M-1, or in parallel via Q contact pads where Q is the first multiple of M which is equal to or larger than N+M-1, the integrated circuit then also comprising a parallel to serial converter circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.