Instruction preprocessor for conditionally combining short memory instructions into virtual long instructions
US5163139A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 1990 |
| Grant date | Nov 10, 1992 |
| Priority date | — |
| Expiry date | Aug 29, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An instruction memory apparatus for a data processing unit stores a sequence of instructions. At each instruction fetch cycle, two sequentially adjacent instructions are accessed. An instruction preprocessing unit, coupled to the internal instruction memory, combines the two sequentially adjacent instructions into a single long instruction word when the two instructions meet predefined criteria for being combined. The first of the two instructions is combined with a no-operation instruction to generate a long instruction word when the predefined criteria are not met. In that case, the second instruction [may be accessed again] is used during the next instruction fetch cycle as the first of the two sequentially adjacent instructions to be processed during that next instruction fetch cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.