Two-level branch prediction cache
US5163140A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 2, 1992 |
| Grant date | Nov 10, 1992 |
| Priority date | — |
| Expiry date | Mar 2, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3848
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved branch prediction cache (BPC) scheme that utilizes a hybrid cache structure. The BPC provides two levels of branch information caching. The fully associative first level BPC is a shallow but wide structure (36 32-byte entries), which caches full prediction information for a limited number of branch instructions. The second direct mapped level BPC is a deep but narrow structure (256 2-byte entries), which caches only partial prediction information, but does so for a much larger number of branch instructions. As each branch instruction is fetched and decoded, its address is used to perform parallel look-ups in the two branch prediction caches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.