Combining switch for reducing accesses to memory and for synchronizing parallel processes
US5163149A · kind A · utility
23Cited by
28References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 2, 1988 |
| Grant date | Nov 10, 1992 |
| Priority date | — |
| Expiry date | Nov 2, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17375
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A combining switch that reduces memory accesses, synchronizes parallel processors and is easy to implement, is achieved by configuring a plurality of parallel processing nodes in a ring arrangement and by implementing a synchronizing instruction for the switch that facilitates, rather than inhibits, parallel processing. According to the preferred embodiment of the invention the ring is a token ring and the synchronizing instruction is a Fetch-and-Add instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.