Complementary bipolar and CMOS on SOI

US5164326A · kind A · utility

Assignee

• Motorola, Inc. · US

Inventors

• Juergen A. Foerstner · Mesa, US
• Bor-Yuan Hwang · Chandler, US
• John E. Schmiesing · Round Rock, US

Key dates

• Filing date: Mar 30, 1992
• Grant date: Nov 17, 1992
• Expiry date: Mar 30, 2012

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S148/15

Abstract

A method for fabricating BiCMOS on SOI. An SOI wafer (14) with an oxide layer (17) and a nitride layer (16) has areas isolated by a LOCOS or mesa isolation (13). A region (15) is defined for CMOS structures from which the insulating layers (17,16) are removed. A gate oxide (21), a polycrystalline silicon layer (22), and a second insulating layer (23,24) is formed. A region for emitters (26) is defined and nitride deposited to form a spacer (27). An oxide layer (28) is grown over the polycrystalline silicon (22) within the emitter region (26). The wafer (14) is etched to the underlying monocrystalline silicon (18) forming base contacts (31). A polycrystalline silicon spacer (36) is formed from a second polycrystalline layer (43) and an oxide spacer (40) is deposited. A region for bipolar collectors (32) and CMOS areas (34) is defined and a spacer (38) deposited.