Programmable CMOS flip-flop emptying multiplexers
US5164612A · kind A · utility
Inventor
Key dates
| Filing date | Apr 16, 1992 |
| Grant date | Nov 17, 1992 |
| Priority date | — |
| Expiry date | Apr 16, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/0372
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A CMOS flip-flop circuit that includes master and slave inverter latches, a pass transistor for opening and closing access of the master latch input to an input signal D, and a special driver circuit between the master and slave latches to pull the input of the slave latch either up or down depending on the logic level of the master latch output. The pass transistor and driver circuit are responsive to a control signal, supplied by complementary clock signals or by multiplexers that select either the clock signals or a fixed logic high signal, to activate a conductive path to the inputs of respective master and slave latches. The driver circuit includes four transistors connected, so that first and second transistors are in series and third and fourth transistors are in series, to form two parallel paths from two logic level sources to the slave latch input. First and third transistors are driven by the master latch output, while second and fourth transistors are driven by the control signal to the drive circuit. The two logic level sources connected to the first and third transistors may be fixed logic high and low voltage levels for conventional flip-flop operation or to multiple…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.