Reset monitor
US5164613A · kind A · utility
24Cited by
8References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 16, 1991 |
| Grant date | Nov 17, 1992 |
| Priority date | — |
| Expiry date | Jul 16, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Reset monitor for detection of power failure and external reset for devices such as microprocessors with the reset monitor providing a single settling time hold down of a reset signal. Preferred embodiments include bandgap reference with high current side compensating resistor, bond out options for analog parameter selection, glitch free state machine control of both detections, and external pushbutton debouncing both depression and release.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.