Superconducting gate array cells
US5164618A · kind A · utility
7Cited by
2References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 14, 1991 |
| Grant date | Nov 17, 1992 |
| Priority date | — |
| Expiry date | Aug 14, 2011 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S505/859
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Superconducting timed gate array cells for use in single-rail logic circuits are provided by adding inputs to modified variable threshold logic (MVTL) timed inverter circuits. Data signals which are inphase with a first phase of a power source are coupled to gate array cells in which Josephson junction bias current is provided by a second phase of the power source. NOR, NAND, 2NOR-OR and 2NAND-AND circuits are disclosed for use as building blocks in the production of specialized digital logic circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.