Fast overflow and underflow limiting circuit for signed adder
US5164914A · kind A · utility
13Cited by
5References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 3, 1991 |
| Grant date | Nov 17, 1992 |
| Priority date | — |
| Expiry date | Jan 3, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/49921
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a signed binary adder circuit, limiter control circuitry detects underflow and overflow conditions, and controls combinatorial result limiter circuits in each bit position to limit the result to predetermined values under such conditions, respectively. The limiter circuits employ OR-AND-INVERT logic (OAI) to provide the appropriate result bits without clock delay for fast limiting.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.