Cascaded driver circuit
US5164970A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 1990 |
| Grant date | Nov 17, 1992 |
| Priority date | — |
| Expiry date | Dec 14, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G3/3685
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A cascaded driver circuit has two or more stages connected to a common serial data signal line and a common clock pulse signal line. Each stage has a counter circuit for dividing the frequency of the clock pulse signal and an enable latch circuit for latching an enable signal, received from the preceding stage, in response to the divided clock pulses. A data latching circuit in each stage latches serial data in response to the clock pulse signal, starting when the enable signal is latched and stopping when a first number of bits of serial data have been latched. An enable output circuit in each stage sends an enable signal to the next stage when the data latching circuit has latched a second number of bits, the second number being at least two less than the first number.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.