Patent · US Expired

Parallel processing development system with debugging device includes facilities for schematically displaying execution state of data driven type processor

US5165036A · kind A · utility

28Cited by

17References

21Claims

0Family size

Assignees

SHARP KABUSHIKI KAISHA · JP
Mitsubishi Electric Corporation · JP

Inventors

Souichi Miyata · Nara, JP
Satoshi Matsumoto · Hamamatsu, JP
Shin'ichi Yoshida · Osaka, JP
Toshiya Okamoto · Kyoto, JP
Takeshi Fukuhara · Kasai, JP
Shinji Komori · Itami, JP
Tetsuo Yamasaki · Kitakyushu, JP
Kenji Shima · Nishinomiya, JP

Key dates

Filing date	Jan 29, 1990
Grant date	Nov 17, 1992
Priority date	—
Expiry date	Jan 29, 2010

Classification

Technology area (CPC G)Physics
CPC primaryG06F11/3636
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A parallel processor developing system comprises a control computer, an interface portion, a processing element, a tracer portion and a display portion. The processing element comprises a data driven type processor. The interface portion stores data packets supplied from the control computer and applies the data packets to the processing element at a predetermined time interval. The tracer portion stores the data packets supplied from predetermined ports of the processing element together with time information. The display portion displays storage contents of the tracer portion.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.