Semiconductor chip packages
US5165067A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 1991 |
| Grant date | Nov 17, 1992 |
| Priority date | — |
| Expiry date | Oct 15, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor chip package comprising at least one semiconductor chip disposed in a package and a plurality of first and second pins extending from the package, which first pins are electrically connected to the at least one semiconductor chip and are adapted to conduct signals between the at least one semiconductor chip and external circuitry, the first pins being divided into a plurality of groups, each group representing a respective signal type, and which second pins are not electrically connected to the at least one semiconductor chip, the first pins of at least one group and the second pins being asymmetrically disposed along edges of the package and the remaining groups of first pins being symmetrically disposed along edges of the package. The invention also provides a stacked module of the semiconductor chip package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.