Multi-emitter BICMOS logic circuit family with superior performance
US5166552A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 1991 |
| Grant date | Nov 24, 1992 |
| Priority date | — |
| Expiry date | Mar 8, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/215
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A multi emitter multi input BICMOS NAND circuit (30) is provided wherein an output node OUT connected to an output terminal (33) is coupled between pull up (31) and pull down (32) blocks. According to one embodiment of the present invention, the pull up block (32) is comprised of a plurality of identical basic cells, each comprised of a CMOS inverter (C31, C32) driving an NPN pull up transistor (T31, T32) mounted as an emitter follower. Logic signals (A31, A32) are applied on the inputs of the inverters (C31, C32), and the inverted signal (A31, A32) is available at the emitter of the emitter follower which corresponds to the output of the cell. All outputs are tied altogether to perform an OR function and are connected to said output terminal (33) to have a multi emitter like circuit. The pull down block (32) in this embodiment is comprised of 2 FETs (F31, F32) serially connected between said output node OUT and a discharge device such as a feedback NFET (Z) the gate of which is connected to said output node OUT. These 2 FETs are for driving a NPN pull down transistor (T), the collector of which is also connected to the output node OUT. The invention includes a number of other embo…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.