Methods and apparatus for facilitating scan testing of asynchronous logic circuitry
US5166604A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 1990 |
| Grant date | Nov 24, 1992 |
| Priority date | — |
| Expiry date | Nov 13, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31707
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Scan testing of asynchronous logic circuitry is facilitated by gating off the asynchronous inputs to flip-flops during scan testing. If desired, the asynchronous inputs which are gated off in this manner may themselves terminals or scan registers during testing. Alternatively, the asynchronous inputs which are gated could be tested by selectively enabling the signals at strategic points during scan testing. The number of input terminals required to control the test mode may be reduced by providing registers for storing test control signals applied to normal input terminals at the beginning of a test cycle. Once these test control signals are stored, the normal input terminals are free to return to their normal use.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.