Dynamic biasing for class A amplifier
US5166636A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 9, 1991 |
| Grant date | Nov 24, 1992 |
| Priority date | — |
| Expiry date | Jul 9, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/3088
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A Class A amplifier has a balanced input circuit including first and second input transistors to receive inverting and non-inverting inputs and to provide an output signal on the collector of the first input transistor. First and second load transistors are associated with the input transistors, the bases of the load transistors being connected to the collector of the second input transistor. An output circuit has source and sink output NPN transistors connected to receive the output signal from the first input transistor, and a circuit is provided for dynamically biasing at least one sink output transistor to have a minimum biasing current in a quiescent state, and increased biasing current in a current sink state. The circuit for dynamically biasing the output transistors has a pair of bias NPN transistors with their collector-emitter paths connected in series, and with the base of one connected to receive the output of the first input transistor. The base of the other bias transistors is connected to the emitter of the one bias transistor and to the base of the sink output transistor. The first and second bias transistors are sized to balance the load seen by the first and secon…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.