Fault detection and bypass in a sequence information signal processor
US5168499A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 1990 |
| Grant date | Dec 1, 1992 |
| Priority date | — |
| Expiry date | Oct 2, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/83
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention comprises a plurality of scan registers, each such register respectively associated with a processor element; an on-chip comparator, encoder and fault bypass register. Each scan register generates a unitary signal the logic state of which depends on the correctness of the input from the previous processor in the systolic array. These unitary signals are input to a common comparator which generates an output indicating whether or not an error has occurred. These unitary signals are also input to an encoder which identifies the location of any fault detected so that an appropriate multiplexer can be switched to bypass the faulty processor element. Input scan data can be readily programmed to fully exercise all of the processor elements so that no fault can remain undetected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.