Data sorting circuit
US5168567A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 1989 |
| Grant date | Dec 1, 1992 |
| Priority date | — |
| Expiry date | May 30, 2009 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S707/99936
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for software performance analysis implements a balanced binary tree in hardware. This circuit consists of a number of "levels", each containing two (sets of) latches, a RAM, and a digital comparator. One of the latches, the data latch, is used to hold the data element being evaluated. The other latch, the results latch, stores partial results based on the comparisons performed on higher levels. The RAM is addressed by the contents of the results latch on the preceding level in combination with the output of the comparator on that same preceding level. The output of the RAM is compared by the digital comparator with the contents of the data latch, to produce an additional bit of results information for the next level. On each level, the RAM is preprogrammed with twice as many midpoint addresses as is the RAM on the preceding level. The outcome of the comparison done on any particular level is used, along with the results from preceding levels, as an address to access a RAM on the next level. Eventually, the last level is reached and there is only one range for each address generated on that level. This address is then applied to a count-holding RAM, and the contents of tha…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.