Error tolerant 3x3 bit-map coding of binary data and method of decoding
US5170044A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 9, 1990 |
| Grant date | Dec 8, 1992 |
| Priority date | — |
| Expiry date | Nov 9, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06K19/06037
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for the representation of binary data. Each bit of binary data corresponds to one of two representations, where each representation is a 3.times.3 array of cells. In a first representation five cells of the array are asserted and four cells are not asserted, and the second representation is complementary to the first representation. In the first representation the asserted cells are the four corner cells and the central cell of the 3.times.3 array. These representations are preferred since they minimize the possibility of long runs of contiguous cells having the same value in an indicia representing a plurality of data bits; which is useful to synchronize scanning of the indicia. An error in the transcription of a data bit is detected by comparison of a nominal representation with the received 3.times.3 array in determining the number of cells which differ between the nominal and the received representations. If the number of cells which differ between the nominal and the received representations is less than five, the received 3.times.3 array is assumed to correspond to the selected nominal representation, otherwise the received array is assumed to correspon…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.