Master-slave clocked flip-flop circuit
US5170074A · kind A · utility
27Cited by
1References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 12, 1991 |
| Grant date | Dec 8, 1992 |
| Priority date | — |
| Expiry date | Mar 12, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/35625
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A flip-flop of a master-slave type of a CMOS structure having no P channel transistor between nodes of the master flip-flop and of the slave flip-flop is provided. Only one P channel MOS transistor is existent in a route of the current controlling a rise time and a trail time of output signals, so that it is possible to function at a high speed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.