Mask ROM having monocrystalline silicon conductors
US5170227A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 1990 |
| Grant date | Dec 8, 1992 |
| Priority date | — |
| Expiry date | Mar 14, 2010 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/91
Abstract
A method for producing a mask ROM having an array of memory cells in which pn junctions obtained by introducing P-type impurities by ion implantation onto the surface of an N-type electrically conductive layers obtained in turn by introducing N-type impurities into the polysilicon layers are formed as memory cells in a matrix configuration. The polysilicon layers that are to be rendered into the N-type electrically conductive layers are previously monocrystallized by laser annealing. In this manner, the N-type electrically conductive layers into which P-type impurities are introduced by ion implantation at the time of formation of the pn junction are turned into a monocrystalline layer so that the surface of the N-type electrically conductive layers may be uniformly and easily converted into the P-type by this ion implantation. In short, the junction surface of the pn junction used as the memory cell becomes uniform. In this manner, the memory cell having desirable pn junction properties, that is, suited for practical application, may be produced easily.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.