Vector bit-matrix multiply functional unit
US5170370A · kind A · utility
59Cited by
17References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 21, 1990 |
| Grant date | Dec 8, 1992 |
| Priority date | — |
| Expiry date | Nov 21, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus provides bit manipulation of data in vector registers of a vector register computer system. Matrix multiplication is accomplished at a bit level of data stored as two matrices in a vector computer system to produce a matrix result. The matrices may be at least as large as 64 bits by 64 bits and multiplied by another 64 by 64 matrix by means of a vector matrix multiplication functional unit operating on the matrices within a vector processor. The resulting data is also stored at a 64 bit by 64 bit matrix residing in a resultant vector register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.