System having constant number of total input and output shift registers stages for each processor to access different memory modules
US5170483A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 8, 1989 |
| Grant date | Dec 8, 1992 |
| Priority date | — |
| Expiry date | Aug 8, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8007
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A central unit for a data-processing system having a high degree of parallelism. This central unit includes a number of basic processors sending requests to a number of modules in receiving responses from those modules. To simplify the interconnection between the modules and the processors when their number increases, the invention is characterized wherein the requests sent from each processor are transmitted to the input of each of said modules via an input shift register, wherein the response coming from each of the said modules are transmitted to the input of each processor via an output shift register, wherein for any provided processor, the number of stages of said input shift register making it possible to access the modules is different for each of the modules and wherein for any processor, the total number of stages belonging to the input and output shift registers associated with one of the said modules is constant and independent of the module and processor in question.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.