Method of manufacturing a semiconductor device having interconnetion patterns
US5171714A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 13, 1992 |
| Grant date | Dec 15, 1992 |
| Priority date | — |
| Expiry date | Apr 13, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor device is disclosed which may form a very minute interconnection pattern having line width less than that of an interconnection pattern formed by a photolithography technique. In the method of manufacturing a semiconductor device, after patterning by a photolithography technique polysilicon layer 3a and nitride layer 4a laminated in order on semiconductor silicon substrate 1, an oxide film is formed in a self-alignment manner in the polysilicon layer by thermal oxidation treatment at a high temperature and a nitride film is removed by etching back the whole surface. The polysilicon layer is divided into two by carrying out etching with the oxide film used as mask. It is possible to form two interconnection patterns in the space for one interconnection pattern formed by a photolithography technique using such a manufacturing method.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.