Five-volt tolerant differential receiver
US5172016A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 28, 1991 |
| Grant date | Dec 15, 1992 |
| Priority date | — |
| Expiry date | Jun 28, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018528
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A differential, CMOS receiver includes a transistor, coupled in parallel with an input transistor, which limits voltage differentials across an input transistor. A corresponding, similarly sized transistor balances current loading in a differential transistor. The transistor in parallel with the input transistor, whose drain is coupled directly to the power supply, quickly pulls the input transistor source and drain up to power supply voltage on an input transient from logical zero to a logical one which exceeds the power supply voltage. Another transistor coupled between the output node and the power supply rail defeats differential amplifier action when the input voltage is high out of its normal range.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.