Asynchronous parallel status comparator
US5172091A · kind A · utility
Inventors
Key dates
| Filing date | Apr 1, 1991 |
| Grant date | Dec 15, 1992 |
| Priority date | — |
| Expiry date | Apr 1, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/607
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus for matching asynchronously received signals and determining whether two or more out of a total number of possible signals match. The apparatus comprises, in one embodiment, an array of sensors positioned in discrete locations and in communication with one or more processors. The processors will receive signals if the sensors detect a change in the variable sensed from a nominal to a special condition and will transmit location information in the form of a digital data set to two or more receivers. The receivers collect, read, latch and acknowledge the data sets and forward them to decoders that produce an output signal for each data set received. The receivers also periodically reset the system following each scan of the sensor array. A comparator then determines if any two or more, as specified by the user, of the output signals corresponds to the same location. A sufficient number of matches produces a system output signal that activates a system to restore the array to its nominal condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.