Semiconductor memory device having error checking and correcting circuit and operating method therefor
US5172339A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 21, 1990 |
| Grant date | Dec 15, 1992 |
| Priority date | — |
| Expiry date | Aug 21, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device having an error checking and correcting (ECC) circuit is disclosed. This memory device includes data lines (10-21) from an ECC data generation circuit and bit lines (30-41) connected to the adjacent memory cells in a memory array (1), which are selectively connected at specified connecting portions (51, 52). When predetermined test data is inputted in order to detect undesired contact or interference between the memory cells, checker pattern data can be written in all the memory cells. Thus, despite the fact that the memory device includes an ECC circuit, a complete and easy memory cell checking is carried out.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.