Single channel serial data receiver
US5172397A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 5, 1991 |
| Grant date | Dec 15, 1992 |
| Priority date | — |
| Expiry date | Mar 5, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A data latch circuit, a gated clock circuit and a delay line circuit for receiving and decoding combined serial data and clock information are disclosed. The data latch circuit, by eliminating the need to use a clear signal, has no "blind spot" with regards to incoming data and can therefore accept data at a faster rate than known circuits. The gated clock also does not utilize the clear signal of the known art and can therefore produce a higher frequency clock pulse. The delay line prevents pulse compression and pulse collapse by means of a flip-flop and exclusive OR means. The circuits may be used together in a receiver for receiving combined serial data and clock information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.