Precision FET control loop
US5172409A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 2, 1990 |
| Grant date | Dec 15, 1992 |
| Priority date | — |
| Expiry date | Jul 2, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04M3/005
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A telephone line card circuit includes an operational amplifier circuit having first and second inputs and an output. A field-effect transistor circuit has first, second and control electrodes, the control electrode is coupled to the output of the operational amplifier circuit, the first electrode is coupled to the TIP/RING terminal, and the second electrode is coupled to the second input of the operational amplifier circuit. A first resistor is coupled between the TIP/RING terminal and the first input of the operational amplifier circuit. A second resistor is coupled between the first input of the operational amplifier circuit and a terminal of the circuit whereby the terminal of the circuit is typically coupled to a supply voltage terminal. A third resistor is coupled between the second input of the operational amplifier circuit and the terminal of the circuit such that the precision of the ratio of the resistance of the field-effect transistor circuit to the third resistor is determined by the precision of the ratio of the first resistor to the second resistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.