Frequency detector system on a digital phase locked loop
US5173927A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 1990 |
| Grant date | Dec 22, 1992 |
| Priority date | — |
| Expiry date | Nov 29, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03D13/001
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A frequency detection system is based on a digital phase locked loop, the detection system being especially suitable for use in noisy environments like supervisory audio tone (SAT) detection in AMPS and TACS mobile telephone systems. In addition to the digital phase locked loop (4), the frequency detection system according to the invention incorporates a detector circuit (5), which comprises a detection timer (6) and two phase detectors VI1 (7) and VI2 (8). The timer (6) forms a detection sequence of desired length, at the end of which the output signal (SATVAL) of the detector circuit is updated. The first phase detector VII (7) has a phase window in which it counts those falling edges of the synchronized input signal (SSAT) that coincide with the window. The second phase detector VI2 (8) also has a phase window of its own in which it counts those falling edges of the synchronized input signal (SSAT) that coincide with its window. The phase windows are made up of the basic output signal of the digital phase locked loop (SO1) and its 2nd, 4th, and 8th harmonics (SO2, SO4 and SO8). If at the end of a detection sequence the counter of the first phase detector VII (7) exceeds, and the…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.